In one conventional data storage arrangement, a host includes a plurality of host processors coupled to a host bridge/bus system. The host bridge/bus system is also coupled via a proprietary bus link to an input/output (I/O) bridge. The I/O bridge is coupled to an I/O processor via a first industry standard bus. The I/O processor includes a bridge that couples the first industry standard bus to a second industry standard bus. An I/O controller is coupled to the second industry bus, and is also coupled to a redundant array of inexpensive disks (RAID). Each of the industry standard buses is compatible with the same bus protocol.
In this conventional arrangement, the host processors, host bridge/bus system, I/O bridge, and I/O processor each comprise a separate, respective integrated circuit chip. In operation, a host processor may issue to the I/O processor, and/or the I/O processor may issue to a host processor data and/or commands. Such data and/or commands propagate through the I/O bridge. This introduces propagation delay in the transmission, and/or reduces the maximum possible transmission bandwidth, of such data and/or commands in this conventional arrangement.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.